Complementary metal oxide semiconductor (CMOS) devices built on an extremely thin semiconductor-on-insulator (SOI) substrate has been one of the viable options for continued scaling of CMOS technology to 22 nm node and beyond. For viable use in the 22 nm node, ETSOI wafers require an extremely thin SOI layer having a thickness of about 60 Angstroms (Å) or less with a variation in the thickness of about +/−6 Å or less. The electrical characteristics of devices formed using ETSOI technology are influenced by the thickness of the ETSOI layer. For example, the threshold voltage (Vt) of a device formed using ETSOI is primarily determined by the thickness of the ETSOI layer. As such, any variation in the thickness of an ETSOI layer of wafer can lead to undesirable variations in threshold voltage. For example, when many chips are created from a 300 mm ETSOI wafer, variations in the thickness of the ETSOI layer can result in threshold voltage variation from chip to chip, or within a single chip.
Wafer thinning is a known technique for creating an ETSOI wafer from an SOI wafer. However, conventional wafer thinning processes produce an ETSOI layer with too much within-a-wafer thickness variation for the desired 22 nm node. For example, a known wafer thinning technique is to oxidize a bonded or SIMOX (e.g., separated by ion implantation of oxygen) SOI wafer in a furnace and then wet etch the oxide. However, this method does not improve SOI layer thickness variation, but rather simply transfers any thickness variation that is initially present in the SOI layer to the ETSOI layer. For example, known oxidation-based wafer thinning techniques are capable of producing an ETSOI layer having a thickness of about 60 Å, but with a thickness variation of about +/−20 Å. As such, conventional wafer thinning techniques do not provide the ETSOI layer thickness uniformity required by the 22 nm node.
Corrective etching is another known wafer thinning technique that utilizes gas cluster ion beam (GCIB) etching to thin the SOI layer of a wafer. Corrective etching is capable of thinning an SOI layer to a thickness of less than 60 Å with a thickness variation of less than +/−6 Å. However, GCIB etching produces high energy chemical and physical reactions at the surface of the wafer, and these reactions leave undesirable surface damage on portions of the wafer that remain after the etch is complete.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.